High density embedded memory used for microprocessor caches and system on a chip (SOC) solutions for devices such as cellular telephones are becoming more prevalent. Further, memory cell size has been continually scaled down at each technology node to pack more bits for a given die size and cost. With reduced cell area, it is becoming increasingly difficult to maintain balance among stability, performance, and leakage current of the bitcell.
Embedded memory devices are often formed of static random access memory (SRAM) bitcells. Each bitcell (also referred to as a “cell”) uses three transistor pairs, namely, access or wordline transistors, pull-down transistors, and pull-up transistors. The pull-up transistors may be implemented using p-channel metal oxide semiconductor (PMOS) transistors. The pull-down and access transistors may be implemented using n-channel MOS (NMOS) transistors. The bitcell may be implemented using a bistable flip-flop. The flip-flop includes the described pull-up and pull-down transistors, which may be accessed using the access transistors. A direct current (DC) supply voltage is applied to the flip-flop to retain data stored in it.
One problem associated with SRAM cells is leakage currents. These currents include a gate oxide leakage current and a sub-threshold leakage current. Individually, the leakage of one cell is relatively small. However, an SRAM array may include millions of cells. Thus, the leakage currents of multiple cells can result in substantial leakage for the array. This leakage is compounded with each new generation of SRAMs, as the smaller physical size of the cells enables more cells to be placed in an array. One solution to leakage currents is use of smaller voltages.
However, degraded memory performance can occur when reduced supply and bitline voltages are used to access and write data to the bitcell. Such lower voltages are susceptible to noise and other problems, and may lead to slower read times and/or inaccurate data, such as toggling of the data in the bitcell.
Still further, SRAMs can suffer from stability problems. Such stability problems include possible toggling of data in a bitcell, as a node between a pull-up and a pull-down device can vary from its target potential of a logic low value or a logic high value. As the potential of the node varies, stability is reduced and the state of the flip-flop forming the bitcell can be toggled. Accordingly, the transistor pairs are sized differently to optimize performance and stability. For example, the beta (defined as the width over length of a transistor) of the pull-down transistor is traditionally larger than that of the wordline transistor. In other words, a beta ratio (betapull-down/betawordline) between the devices is traditionally maintained at a value greater than 1 to guarantee stability. The requirement to size each of the SRAM transistor pairs differently further creates scaling challenges. As a result, SRAM memory design is typically a compromise between performance, stability, and size issues. A need thus exists for improved memory technology.